Novel cell design and process for making dynamic random access memory (DRAM) having one or more gigabits of memory cells

ABSTRACT

A method and novel DRAM cell design are described for making DRAM devices with more than a Gigabit memory cells. After forming the FETs and polycide word lines with a cap oxide and sidewall spacers, a thin diffusion protection oxide is deposited and openings are formed for contacts to the substrate. A conductively doped first polysilicon layer is deposited and polished back to the cap oxide. The first polysilicon remaining in the recesses between word lines is patterned to form first plug that are auto self-aligned (zero alignment error) to the word lines to achieve a very high density (Gigabit) memory. A planar first insulating layer with openings for bit lines is formed. Polycide bit lines are formed having a Si3N4 cap layer and sidewall spacers. Contact openings are selectively etched to first in the first insulating layer to first plugs and self-aligned aligned to the bit lines. A doped second polysilicon layer is deposited and polished back to the Si3N4 cap layer, and the remaining polysilicon between bit lines is patterned to form auto self-aligned capacitor node contacts to further increase memory cell density. A second insulating layer is deposited, in which DRAM capacitors are formed to complete the high density of memory for Gigabit DRAM devices. The auto self-aligned process eliminates critical photomask alignment and etching.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to integrated circuit semiconductordevices, and more particularly to a method for fabricating dynamicrandom access memory (DRAM) devices having one or more Gigabits ofmemory cells. This novel method improves the memory-cell density usingauto self-aligning techniques while reducing electrical shorts betweenthe word lines and polysilicon plug contacts. The method also reducescapacitor node leakage currents, parasitic capacitance. Also reduced isthe electrical shorts between the closely spaced polysilicon plugs viakeyholes (voids) in the interpolysilicon oxide (IPO) due to poor gapfilling with the IPO.

[0003] 2. Description of the Prior Art

[0004] As integrated circuit density increases, it becomes increasingdifficult to manufacture ultra large scale integrated (ULSI) circuitsbecause of process limitations. This problem is particularly acute formaking future DRAM devices having more than a Gigabit of memory cells.These process limitations are best understood by referring to theconventional DRAM structure in the prior art FIGS. 1A and 1B. FIG. 1Ashows a portion of a partially completed DRAM cell. Typically a shallowtrench isolation (STI) 12 is formed in a silicon substrate 10surrounding and electrically isolating device (memory cell) areas. abarrier layer 13, such as silicon nitride (Si₃N₄), is deposited andpatterned to form openings over the device areas and a gate oxide 14 isgrown on the substrate 10 for field effect transistors (FETs). A dopedpolysilicon layer 16, a refractory metal silicide layer 18 and aninsulating cap layer 20 is deposited and patterned to form word lines(layers 16, 18) over the STI 12 while concurrently forming FET gateelectrodes over the thin gate oxide 14. Doped source/drain areas 17(N)are formed adjacent to the gate electrodes by ion implantation and aconformal insulating layer is deposited and anisotropically plasmaetched back to form sidewall spacers 22 on the sidewall of the FET gateelectrodes (patterned layer 16 and 18). Next an insulating layer 24 isdeposited and polished back to form the first interpolysilicon oxidelayer (IPO-1) and a photoresist mask and plasma etching are used to etchcontact openings that extend over the FET gate electrodes (self-aligned)and down to the source/drain areas. One problem encountered in thisconventional self-align process is damage to the source/drain areas 17when the contact holes are plasma etched. Another problem is theoveretching of the cap oxide layer 20, as depicted at point B in FIG.1A, which can result in shorts to the FET gate electrodes when thecontact holes are filled with a doped polysilicon (poly plugs) to makeelectrical contacts. Also the poly plugs also overlap the gate electroderesulting in increased parasitic capacitance, resulting in an increasedRC time constants and reduced circuit speed. Another problem encounteredis poor gap filling between the closely spaced word lines (patternedlayers 16, 18 & 20) having high aspect ratios, as depicted at point A inFIG. 1A. When closely spaced contact openings 2 are etched in theinsulating layer 24 and into the voids A between the word lines shortscan occur when the contact holes 2 are filled with polysilicon 26 toform the poly plugs. A major shortcoming of the conventional process isthe need to align the contact hole extending over the FET gateelectrodes, and requires relaxing the alignment rules which makes itdifficult to achieved the required density for Gigabit DRAM chips. Stillanother problem with the conventional process is depicted in FIG. 1B forconcurrently making borderless contacts 4 to the silicon substrate, thatis contacts that extend over the shallow trench isolation (STI). Whencontact openings 2 are etched in the insulating layer 24 it is necessaryto use an etch stop layer 13 (Si₃N₄) to prevent over etching the STI atthe edge and damaging the contact. However, this requires additionalprocess steps.

[0005] Numerous methods of making DRAM devices with improved electricalcharacteristics while increasing memory cell density have been reported.One method is described by Huang in U.S. Pat. No. 5,783,462 in whichexternal contacts for testing stacked capacitors DRAM, but does notaddress the above problem. Another method for making DRAM devices withincreased density and improved sign-to-noise ratio is described by Keethin U.S. Pat. No. 5,864,181 but also does not address the above concerns.Cherng in U.S. Pat. No. 5,837,577 teaches a method for making DRAMcapacitor node contacts self-aligned to the bit lines but and also doesnot address the above problems.

[0006] However, there is still a need in the industry to provide animproved process with novel cell design that is applicable to DRAMshaving more than a Gigabit of memory cells. Further while reducing thenarrow spacings for Gigabit DRAMS by minimizing the alignment toleranceground rule, it is also necessary to reduces parasitic capacitance,capacitor node leakage currents, and electrical shorts between closelyspace polysilicon plug contacts to achieve an acceptable circuitperformance and an acceptable product yield.

SUMMARY OF THE INVENTION

[0007] A principal object of the present invention is to formcapacitor-over-bit line (COB) dynamic random access memory (DRAM)devices with increased memory cell density for future DRAM devices withone or more Gigabits of memory cells. The increase in cell density isachieved by using a double auto self-aligned polysilicon contact plugstechnique.

[0008] A second objective of this invention is to form thesehigh-density memory cells with reduced electrical shorts, reducedparasitic capacitance to word lines and reduced capacitor node leakagecurrent by reducing plasma etch damage at the substrate contacts.

[0009] A third objective of this invention is to form theinterpolysilicon oxide (IPO) gap filling after the auto-self-alignedpolysilicon plugs are formed. This prevents the polysilicon plugs fromshorting through keyhole channels (voids) in the IPO while the keyholecavities between plugs further reduce intralevel capacitance.

[0010] Still another objective of this invention is to provide a verycost-effective manufacturing process.

[0011] This novel invention is a method for making DRAM devices with oneor more Gigabit of memory cell. The method begins by providing asemiconductor substrate, such as a P⁻ doped single-crystal siliconhaving a <100> crystallographic orientation. A relatively thick FieldOXide (FOX) is formed that surrounds and electrically isolates deviceareas on the substrate for the DRAM memory cells. One conventionalmethod of forming the field oxide areas is by a shallow trench isolation(STI) method, as commonly practiced in the industry. Field effecttransistors (FETs) are formed next by growing a thin gate oxide on thedevice areas. A first polycide layer is formed by depositing a heavilyN⁺ doped polysilicon layer and a refractory metal silicide layer. Aninsulating layer, such as silicon oxide (SiO₂), is deposited to form afirst cap layer on the polycide layer. The cap layer and first polycidelayer are patterned to form the DRAM word lines that also serve as gateelectrodes over the device areas. Next N doped source/drain areas areformed adjacent to the gate electrodes and a conformal insulating isdeposited and anisotropically etched back to form first sidewall spacerson the gate electrode.

[0012] Next a thin conformal diffusion protection oxide layer, such asSiO₂, is deposited and is patterned to form openings where contacts tothe substrate are desired. Then a first conducting layer, preferablycomposed of an N doped polysilicon is deposited and ischemically-mechanically polished (CMP) back to the first cap oxidelayer. A photoresist mask and plasma etching are used to pattern thepolished back first conducting layer to form the first contact plugs forbit lines and for capacitor node contacts. The polish-back results inthe first contact plugs being auto-self-aligned to the gate electrodes.This eliminates the critical alignment requirement for etching theself-aligning contact openings 2 in the conventional process (see FIG.1A) and avoids the damage due to plasma etching in the contact opening.Also the damage to borderless contacts 4 (see prior art FIG. 1B) is alsoavoided. Next a first insulating layer, preferably SiO₂, is depositedand planarized by CMP. Because the first insulating layer is depositedafter the polysilicon plugs are formed, the gaps (voids) formed are notcontinuously open between the closely spaced plugs. This avoids theelectrical shorts, of the conventional process when contact openings areetched in the insulating layer having the keyhole gaps. Bit-line contactopenings are etched in the first insulating layer to the first contactplugs for the bit lines. A second polycide layer and a second cap layer,composed of silicon nitride (Si₃N₄), are deposited and patterned to formthe bit lines. A conformal Si₃N₄ or silicon oxynitride (SiON) layer isdeposited and anisotropically etched back to form second sidewallspacers on the bit lines. Capacitor node contact openings areselectively etched in the first insulating layer to the first contactplugs for forming capacitor node contacts while the Si₃N₄ cap layer andthe second sidewall spacers (SiON) protect the bit lines during etching.A second conducting layer, preferably composed of an N-dopedpolysilicon, is deposited and polished back to the Si₃N₄ second caplayer. The polished back layer is then patterned using a photoresistmask and plasma etching to form second contact plugs for capacitor nodecontacts to the first contact plugs. This second polish back results ina second auto self-aligned contact that eliminates another criticalphotoresist mask alignment an further increases circuit density. Themethod for making this high-density array of DRAM cells is now completedby forming a planar second insulating layer, such as SiO₂. Openings areetched in the second insulating layer over and to the second contactplugs for capacitor bottom electrodes. A conformal third conductinglayer is formed in the openings for the capacitor bottom electrodes anda thin interelectrode dielectric layer and a fourth conducting layer areformed over the capacitor bottom electrodes to form the capacitors andto complete the high-density array of memory cells for Gigabit DRAMdevices.

[0013] The invention also includes a method of integrating into the DRAMprocess an improved borderless self-aligned contact (SAC). This improvedSAC does not need a silicon nitride hard mask to protect the edge of theshallow trench isolation (STI), as in the conventional process when thecontact openings are etched in a thick interpolysilicon oxide (IPO)layer to the silicon substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The objects and advantages of this invention are best understoodwith reference to the attached drawings in the figures and theembodiment that follows.

[0015]FIG. 1 shows a prior-art schematic cross-sectional view of apartially completed DRAM depicting the shortcomings of the conventionaltechnology, and a prior-art schematic cross-sectional view for aborderless self-aligned contact make concurrently that also depicts theshortcomings of the conventional technology.

[0016]FIGS. 2 through 9 show a series of schematic cross-sectional viewswith schematic top views depicting the sequence of process steps formaking the high-density array of memory cells for a DRAM using anauto-self-aligned contact method and the method for concurrently makinga borderless SAC.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0017] The invention is now described in detail for making this array ofhigh-density memory cells for DRAMs having more than a gigabit of memorycells, and for concurrently making improved borderless self-alignedcontacts for DRAM devices on a silicon substrate. The series of crosssectional views in the left portions of FIGS. 2-9 are for making theDRAM cells and is likewise labeled “DRAM” while the right portion ofFIGS. 2-9 are for making the self-aligned contact (SAC) and iscorrespondingly labeled “SAC”. The top views in FIGS. 3B and 4B depictthe only DRAM cell design with the auto self-aligned first polysiliconcontacts plugs self aligned to the word lines and contacting thesubstrate. The top views in FIGS. 7B and 8B depict the auto self-alignedsecond polysilicon plugs to the bit line for completing the capacitornode contact to the underlying first polysilicon plugs.

[0018] Although the process is described for making memory cells forDRAM devices having N-channel FETs as the access transistors on aP-doped substrate, it should also be well understood by one skilled inthe art that by including additional process steps, in addition to thosedescribed in this embodiment, other types of devices can be included onthe DRAM chip. For example, by forming N-well regions in a P-dopedsubstrate, P-channel FETs can also be provided and ComplementaryMetal-Oxide-Semiconductor (CMOS) circuits can be formed therefrom, suchas are required for the peripheral circuits on the DRAM chip andembedded DRAM circuits. Although the method is described in detail formaking auto self-aligned polysilicon plugs, it should also be understoodthat other electrically conducting materials, such as tungsten ortungsten silicide and the like, can be used to form the plugs whenprocess compatible.

[0019] Referring now to FIG. 2, the method begins by providing asemiconductor substrate 10, a portion of which is shown in the Fig. fora partially completed DRAM cell. On the left is the DRAM cell and on theright is the borderless SAC. Typically the substrate is a P⁻ dopedsingle-crystal silicon having a <100> crystallographic orientation.Field OXide (FOX) regions 12 are formed surrounding and electricallyisolating the device areas. One conventional method of forming the fieldoxide regions is by using a shallow trench isolation (STI) method, ascommonly practiced in the industry. Generally the STI is formed byetching trenches in the field oxide regions on the substrate 10 to adepth of between about 2500 and 5000 Angstroms. After forming a thinthermal oxide (not shown) in the trenches, the trenches are filled withan insulating material such a chemical vapor deposited SiO₂, and aremade planar with the surface of the substrate 10, for example, by usinga planarizing plasma etchback or chemical/mechanical polishing (CMP) toform the STI 12. Next, a thin gate oxide 14 of about 15 to 70 Angstromsthick is grown on the device areas.

[0020] Still referring to FIG. 2, a first polycide layer is formed bydepositing a heavily N⁺ doped polysilicon layer 16 and a refractorymetal silicide layer 18. The polysilicon layer 16 is deposited bychemical vapor deposition (CVD) using silane (SiH₄) as the reactant gasand is deposited to a preferred thickness of between about 500 and 2000Angstroms. The polysilicon layer 16 is doped with arsenic (As) orphosphorus (P) by ion implantation after deposition or is doped duringthe CVD polysilicon deposition by adding a dopant gas, such as arsine(AsH₃) or phosphine (PH₃). Layer 16 is preferable doped to aconcentration of between about 1.0 E 20 and 1.0 E 22 atoms/cm³. Thesilicide layer 18 is preferably a tungsten silicide (WSi_(x)) and isalso deposited by CVD using tungsten hexafluoride (WF₆) and SiH₄ and thereactant gases and is deposited to a preferred thickness of betweenabout 500 and 1500 Angstroms. An insulating layer 20, such as siliconoxide (SiO₂), is deposited to form a first cap layer 20 on the polycidelayer 18. The cap layer 20 is deposited by low pressure CVD (LPCVD)using, for example tetraethosiloxane (TEOS) as the reactant gas, and isdeposited to form a relatively thick layer. For example the SiO₂ layer20 is deposited to a thickness of between about 1000 and 2000 Angstroms.The cap layer 20 and first polycide layer (layers 16 and 18) are thenpatterned using conventional photolithographic techniques andanisotropic plasma etching to form the DRAM word lines that also serveas gate electrodes over the device areas. Next N doped source/drainareas 17(N) are formed adjacent to the gate electrodes, for example byion implanting As⁷⁵ or p³¹ ions. Preferably ions are implanted at a doseand energy to achieve a final concentration of between about 1.0 E 17and 1.0 E 18 atoms/cm³. First sidewall spacers 22 are formed on thesidewalls of the gate electrode (patterned layers 20, 18 and 16) bydepositing a conformal insulating layer 22 which is then anisotropicallyetched back. The conformal layer 22 is preferably SiO₂ and is depositedby LPCVD using TEOS as the reactant gas. The layer 22 is thenanisotropically etched back using reactive ion etching (RIE) or a highdensity plasma (HDP) etching to achieve a sidewall spacer width ofbetween about 500 and 100 Angstroms. Next, as shown in FIG. 2, arelatively thin conformal diffusion protection oxide layer 13 isdeposited. Layer 13 is preferably SiO₂ and is deposited by LPCVD usingTEOS as the reactant gas and is deposited to a thickness of betweenabout 100 and 500 Angstroms. Layer 13 is then patterned to form openingswhere contacts to the substrate are desired, such as for theself-aligned contacts (SAC) 1 (right portion of FIG. 2) and over theDRAM cells, as shown in the left portion of FIG. 2. The patterning oflayer 13 is carried out using a patterned photoresist mask (not shown)and wet etching in a dilute solution hydrofluoric acid (HF) and water(H₂O) to provide essentially damage free contacts on the substratesurface. Typically a solution of HF to H₂O of between about 1:100 and5:100 by volume is used to etch layer 13.

[0021] Still referring to FIG. 2, a first conducting layer 24 isdeposited. Layer 24 is preferably composed of an N conductively dopedpolysilicon and is deposited by low pressure chemical vapor deposition(LPCVD) using silane (SiH₄) as the reactant gas. Layer 24 is doped insitu by adding a dopant gas such as arsine (AsH₃) or phosphine (PH₃)during the polysilicon deposition. The layer 24 is preferably doped to aconcentration of between about 1.0 E 20 and 1.0 E 22 atoms/cm₃. Thepolysilicon layer 24 is deposited to a thickness sufficient to fill therecess between the word lines, but more specifically to a thickness ofbetween about 4000 and 7000 Angstroms.

[0022] Referring next to FIG. 3A The polysilicon layer 24 is planarizedback to the cap layer 20. For example, layer 20 ischemically-mechanically polished (CMP) using commercially availablepolishing tools. This CMP results in the remaining N doped polysiliconlayer 24 between the word lines being automatically aligned to the gateelectrodes (patterned layers 16, 18 and 20). This auto self-alignmenteliminates the critical alignment requirement for etching theself-aligning contact openings 2 in the conventional process (see FIG.1A) and avoids the damage due to plasma etching in the contact opening.To better appreciate this process step, a top view after the CMP isdepicted in FIG. 3B in which the cross section in FIG. A is through3A-3A′ of FIG. 3B. The Chem-mech polished backed polysilicon layer 24 isself-aligned to the sidewall spacers 22 on the gate electrodes (16, 18and 20). The top view is only depicted for the DRAM portion of FIG. 3.Since there is no critical alignment and etch step, as in the conventionprocess (see FIG. 1), the circuit density is significantly increased asrequire for Gigabit DRAM devices. Also since the N doped polysilicon 24is deposited prior to depositing ILD layer and etching contact hole, asin the conventional process of FIG. 1, the method avoids plasma etchdamage to the source/drain areas 17(N) in the DRAM cell areas and toborderless contact areas 19(N) as depicted in (SAC) portion of FIG. 3A.

[0023] Referring now to FIG. 4A, a non-critical (alignment) photoresistmasking step and plasma etching are used to pattern the remainingpolysilicon layer 24 to complete the first polysilicon contact plug 24for both the bit lines and capacitor node contacts. The N dopedpolysilicon layer 24 is also patterned, at the same time, to form theborderless self-aligned contacts 24 to the substrate contacts 19(N) andto form interconnections 25, as depicted in the right portion (SAC) ofFIG. 4A. The plasma etching is carried out preferably in a high densityplasma (HDP) etcher using a etching gas mixture containing chlorine(C12) and hydrogen bromide (HBr).

[0024] A top view of the DRAM cell after the process step carried out inFIG. 4A is depicted in FIG. 4B. The borderless contact (SAC) portion ofFIG. 4A is not depicted in the top view. The cross section for the DRAMin FIG. 4A is shown for the region through 4A-4A′ of the top view inFIG. 4B. The photoresist mask is not shown, but the alignment of themask is non-critical in both the x and y directions for etching theplugs 24 depicted in FIG. 4B. Since the patterned photoresist mask canoverlaps the cap insulating 20 an isotropic plasma etch can be used toeffectively remove the polysilicon layer 24 in the recesses between theword lines (16, 18, 20). Further, since the plugs do not extend over theword lines the parasitic capacitance between the plug 24 and the wordline is reduced.

[0025] Still referring to FIG. 4A, a first insulating layer 26 isdeposited and planarized. The insulating layer 26 is preferably SiO₂ ora doped oxide such as borophoso-silicate glass (BPSG). The SiO₂ isdeposited by LPCVD using a reactant gas such as TEOS and the BPSG can beformed by adding a dopant gas during deposition. The insulating layer26, commonly referred to in the industry as the first inter-polysiliconoxide (IPO-1) layer, is preferably planarized by CMP. Because the firstinsulating layer is deposited after the polysilicon plugs 24 are formed,the air gaps (or voids) formed are not continuously open between theclosely spaced plugs 24. This avoids the electrical shorts, of theconventional process where contact openings 2 are etched in theinsulating layer 24 having the keyhole gaps due to poor gap filling, asdepicted in the prior art of FIG. 1. Since the closed voids (point B inFIG. 4A) have an effective relative dielectric k equal to about 1.0, theintralevel parasitic capacitance is also further reduced.

[0026] Referring now to FIG. 5, conventional photolithographictechniques and anisotropic plasma etching are used to etch contactopenings 4 in the first insulating layer 26 to first contact plugs 24for bit lines contacts while the first contact plugs 24 for node contactare protected with photoresist (not shown). After stripping thephotoresist a second polycide layer composed of a N doped polysiliconlayer 28, a refractory metal silicide layer 30 and a second capinsulating layer 32 is deposited and patterned to form the bit lines.The process for forming the bit lines is similar to the process forforming the word lines and is therefore not discussed in detail.However, the preferred thickness of the polysilicon layer 28 is betweenabout 500 and 1000 Angstroms, the thickness of the tungsten silicidelayer 30 is between about 500 and 1500 Angstroms, and the thickness ofthe cap layer 32 is between about 1000 and 2000 Angstroms. However, thesecond insulating cap layer 32 and the sidewall spacers 34 for the bitlines are preferably composed of silicon nitride (Si₃N₄) and/or siliconoxynitride (SiON). For example the Si₃N₄ can be deposited LPCVD usingsilane and ammonia (NH₃) as the deposition gases, and the SiON can bedeposited by adding nitrous oxide (N₂O) during LPCVD.

[0027] Referring now to FIG. 6, the method of making auto self-alignedsecond contact plugs are made for capacitor node contacts that are autoself-aligned to the bit lines is now described. Since the bit lines aretypically formed orthogonal to the word lines on the actual product thecross sectional views in FIGS. 6 through 9 are cross section that arenormal to the cross sections in the earlier FIGS. 2-5, and therefore,the FET gate electrodes are not in view. Referring first to the DRAMportion of FIG. 6, openings 6 are selectively etched in the firstinsulating layer 26 to the first contact plugs 24 for forming capacitornode contacts. Concurrently, contact openings (also labeled 6) for theborderless contacts 19(N) are etched in layer 26 to the polysiliconplugs 24, as depicted in the SAC portion of FIG. 6. The openings in thephotoresist mask (not shown) used for making these contact openings 6extend over the Si₃N₄ cap layer 32 and therefore the openings 6 in layer26 are self-aligned to the bit lines. Typically the contact openings 6are etched using HDP etching or reactive ion etching and a etchant gasmixture which selectively etches the SiO₂ to the Si₃N₄ cap layer. Forexample, one preferred etch gas mixture is a fluorine based gas andoxygen (O₂) which has an etch rate selectivity of SiO₂ to Si₃N₄ of about5:1.

[0028] Still referring to FIG. 6, a second conducting layer 36,preferably composed of an N-doped polysilicon, is deposited by LPCVDusing silane as the reactant gas and is in situ doped with a N typeconductive dopant. For example layer 36 can be dope with phosphorus (P),by adding a dopant gas, such as phosphine (PH₃) during the deposition.Polysilicon layer 36 is doped to a preferred concentration of betweenabout 1.0 E 20 and 1.0 E 22 atoms/cm₃ and is deposited to a thicknesssufficient to fill the recesses between the bit lines (patterned layers28, 30 and 32). More specifically layer 36 is deposited to a thicknessof between about 4000 and 7000 Angstroms.

[0029] Now as shown in FIG. 7A, the polysilicon layer 36 ischemically-mechanically polished back to the Si₃N₄ second cap layer 32.This second polish back results in a second auto self-aligned contact,also labeled 36, that eliminates another critical photoresist maskalignment and further increases the circuit density for Gigabit DRAMdevices. The method forms the capacitor node contacts for the DRAM cellswhile concurrently forms the auto self-aligned contacts 36 to the firstpolysilicon plugs 24 for the borderless contact 19(N), as depicted inthe SAC portion of FIG. 7A. To better appreciate this improved structurea top view of the DRAM cell area is shown in FIG. 7B with the crosssection in FIG. 7A through the region 7A-7A′ in FIG. 7B. The top viewdepicts the polished back polysilicon layer 36 auto self-aligned to theSi₃N₄ or SiON sidewall spacers 34, and therefore self-aligned to the bitlines (patterned layers 28, 30 and 32).

[0030] Referring now to FIG. 8A, The remaining portions of the polishedback polysilicon layer 36 is then patterned using a photoresist mask andplasma etching to form second contact plugs 36 to the first contactplugs 24 for capacitor node contacts. Conventional photolithographictechniques and plasma etching a used to pattern the remainingpolysilicon layer 36, similar to the process used to etch the firstpolysilicon plugs 24. The N doped polysilicon layer 36 is alsopatterned, at the same time, to complete auto self-aligned contacts forthe borderless self-aligned contacts 24 to the substrate contacts 19(N),as depicted in the right portion (SAC) of FIG. 8A. The polysilicon layer36 remaining in the recesses between the bit lines after CMP ispatterned using selective etching in a high density plasma (HDP) etcherthat etches polysilicon selectively to the Si₃N₄ insulating cap layer32, to the sidewall spacers 34, and to the underlying silicon oxidelayer 26. The etch rate ratio of polysilicon to silicon nitride ispreferably greater than about 5:1, and can be achieve using a etch gasmixture having a Cl₂ base.

[0031] The photoresist mask (not shown) used to pattern the secondpolysilicon plugs 36 also extend over the Si₃N₄ insulating cap 32,therefore, the alignment of the photoresist etch mask is not criticaland full advantage of the auto self-alignment is used to achieve GigabitDRAM devices. To better appreciate this auto self-alignment a top viewis shown in FIG. 8B after the patterning of the second polysilicon plugs36. The cross section in FIG. 8A is through the region 8A-8A′ in FIG.8B. Since the second polysilicon plugs 36 are perfectly aligned to thesidewall spacers 34, and therefore aligned to the bit lines (patternedlayers 28, 30 and 32) the maximum density is achieved.

[0032] Still referring to FIG. 8, planar second insulating 38, commonlyreferred to as an interpolysilicon oxide 2 (IPO-2), is formed over thebit lines as an insulating layer. The preferred second insulating layer38 is SiO₂ or a doped glass and is deposited by LPCVD using a reactantgas such a TEOS or TEOS and Ozone (O₃) to form SiO₂. The SiO₂ can bedoped with boron and/or phosphorus during deposition to form a BSG or aBPSG. Insulating layer 38 is then planarized, for example by CMP to havea preferred thickness of between about 5000 and 15000 Angstroms over thebit lines. Since the second insulating layer 38 is deposited after theauto self-aligned polysilicon plugs 36 are formed, any air gaps (voids)due to poor gap fill of layer 38, such as void C depicted in the right(SAC) portion of FIG. 8A do not cause electrical shorts between theplugs 36.

[0033] Referring now to FIG. 9, an array of DRAM stacked capacitor areformed to complete array of memory cells. Conventional photolithographictechniques and anisotropic plasma etching are used to etch openings 8 inthe second insulating layer 38 aligned over the second polysilicon plugs36. The openings 8 are etched selectively to the polysilicon plugs 36using reactive ion etching (RIE) and an etchant gas containing fluorinespecies (e.g. CHF₃) to achieve openings having essentially verticalsidewalls.

[0034] Next a conformal third conducting layer 40 is deposited. Layer 40is preferably a doped polysilicon layer, deposited by LPCVD using, forexample, SiH₄ as the reactant gas, and is doped in situ with phosphorusby adding a dopant gas such as phosphine (PH₃). Layer 44 is deposited toa preferred thickness of between about 500 and 1000 Angstroms, and isdoped to a concentration of between about 1.0 E 20 and 1.0 E 22atoms/cm³. Layer is then etched or polished back to form capacitorbottom electrodes in the openings 8 while moving completely thepolysilicon layer 40 from the top surface of the insulating 38. Then athin interelectrode dielectric layer 42, that has a high dielectricconstant (high-k), is formed on the array of bottom electrode 40. Thedielectric layer 42 is preferably composed of layers of SiO₂Si₃N₄/SiO₂(ONO). The ONO dielectric layer can be formed by first growing a thinthermal oxide (e.g., 5 Angstroms) on the polysilicon bottom electrodes40. A Si₃N₄ layer is deposited by LPCVD. Then a thin SiO₂ is formedusing an oxidation furnace to partially reduce the Si₃N₄ layer to form atop SiO₂ layer that provides a pin-hole-free ONO layer. The effectivethickness of the ONO is about 35 to 50 Angstroms. A fourth conductinglayer 44 is deposited over the capacitor bottom electrodes to completethe capacitors and to form a high-density array of memory cells forGigabit DRAM devices. Layer 44 is preferably an in-situ dopedpolysilicon layer and is deposited by LPCVD using a reactant gas suchSiH₄, and using a dopant gas such as PH₃. The polysilicon layer 44 isdoped N⁺ to a preferred concentration of between about 1.0 E 19 and 1.0E 22 atoms/cm³. The preferred thickness of the polysilicon layer 44 isbetween about 500 and 1000 Angstroms. Layer 44 is then patterned to formthe capacitor top electrodes. A fifth insulating layer 46 is depositedsufficiently thick to electrically insulate the array of capacitors onthe DRAM device prior to subsequent processing to complete the DRAMdevice. Layer 46 is SiO₂, and is deposited by LPCVD.

[0035] While the invention has been particularly shown and describedwith reference to the preferred embodiment thereof, it will beunderstood by those skilled in the art that various changes in form anddetails may be made without departing from the spirit and scope of theinvention.

What is claimed is:
 1. A method for making an array of high-densitymemory cells having auto-self-aligned contacts for DRAM devices on asemiconductor substrate comprising the steps of: forming device areasfor memory cells surrounded and electrically isolated by field oxideareas on said substrate; forming a gate oxide on said device areas;depositing a first polycide layer and a first cap oxide layer andpatterning to form word lines extending over said device areas to formFET gate electrodes, and forming doped source/drain areas adjacent tosaid gate electrodes, and forming first sidewall spacers on said wordlines; forming a patterned diffusion protection oxide with openings forcontacts to said substrate; depositing a first conducting layer;polishing back said first conducting layer to said first cap oxide layerand patterning said first conducting layer to form first contact plugsthat are auto-self-aligned to said gate electrodes; depositing andplanarizing a first insulating layer; etching bit-line contact openingsin said first insulating layer to said first contact plugs; depositing asecond polycide layer and a second cap layer and patterning to form bitlines and forming insulating second sidewall spacers on said bit lines;etching capacitor node contact openings in said first insulating layerto said first contact plugs; depositing a second conducting layer;polishing back said second conducting layer to said second cap layer andpatterning said second conducting layer to form second contact plugs forcapacitor node contacts to said first contact plugs, said second contactplugs auto-self-aligned to said bit lines; depositing and planarizing asecond insulating layer and etching openings for capacitor bottomelectrodes to said second contact plugs; forming a third conductinglayer in said openings for said capacitor bottom electrodes, and formingan interelectrode dielectric layer and a fourth conducting layer to formsaid capacitors and completing said array of high-density memory cells.2. The method of claim 1 , wherein said first polycide layer is composedof a doped polysilicon layer having a thickness of between about 500 and2000 Angstroms and an upper tungsten silicide layer having a thicknessof between about 500 and 1500 Angstroms.
 3. The method of claim 1 ,wherein said first cap oxide layer is silicon oxide deposited bylow-pressure chemical vapor deposition to a thickness of between about1000 and 2000 Angstroms.
 4. The method of claim 1 , wherein said firstsidewall spacers are silicon oxide and have a width of between about 500and 1000 Angstroms.
 5. The method of claim 1 , wherein said diffusionprotection layer is silicon oxide deposited by chemical vapor depositionto a thickness of between about 100 and 500 Angstroms.
 6. The method ofclaim 1 , wherein said first conducting layer is a polysilicon layerdeposited by low-pressure chemical vapor deposition to a thicknesssufficient to fill the recesses between said word lines, and is dopedwith an N type dopant to a concentration of between about 1.0 E 20 and1.0 E 22 atoms/cm³.
 7. The method of claim 1 , wherein said firstinsulating layer is silicon oxide deposited by low-pressure chemicalvapor deposition and is polished to have a thickness of between about3000 and 5000 Angstroms over said FET gate electrodes.
 8. The method ofclaim 1 , wherein said second polycide layer is composed of a dopedpolysilicon layer having a thickness of between about 500 and 1000Angstroms and an upper tungsten silicide layer having a thickness ofbetween about 500 and 1500 Angstroms.
 9. The method of claim 1 , whereinsaid second cap layer is silicon nitride deposited by low-pressurechemical vapor deposition to a thickness of between about 1000 and 2000Angstroms.
 10. The method of claim 1 , wherein said second sidewallspacers are formed by depositing a conformal layer of silicon oxynitrideand anisotropically etching back to form said second sidewall spacershaving a width of between about 500 and 1500 Angstroms.
 11. The methodof claim 1 , wherein said capacitor node contact openings that areselectively etched in said first insulating layer to said first contactplugs are also selectively etched to said second cap layer and saidsecond sidewall spacers to prevent electrical shorts to said bit lines.12. The method of claim 1 , wherein said second conducting layer is adoped polysilicon layer deposited by low-pressure chemical vapordeposition to a thickness sufficient to fill the recesses between saidbit lines, and is doped with an N type dopant to a concentration ofbetween about 1.0 E 20 and 1.0 E 22 atoms/cm³.
 13. The method of claim 1, wherein said second insulating layer is silicon oxide deposited byLPCVD and is planarized to have a thickness of between about 1500 and4000 Angstroms over said bit lines.
 14. A method for making an array ofhigh-density memory cells having auto-self-aligned contacts for DRAMdevices on a semiconductor substrate comprising the steps of: formingdevice areas for memory cells surrounded and electrically isolated byfield oxide areas on said substrate; forming a gate oxide on said deviceareas; depositing a first polycide layer and a first cap oxide layer andpatterning to form word lines extending over said device areas to formFET gate electrodes, and forming doped source/drain areas adjacent tosaid gate electrodes, and forming first sidewall spacers on said wordlines; forming a patterned diffusion protection oxide with openings forcontacts to said substrate; depositing a first conducting layer composedof doped polysilicon; polishing back said first conducting layer to saidfirst cap oxide layer and patterning said first conducting layer to formfirst contact plugs that are auto-self-aligned to said gate electrodes;depositing and planarizing a first insulating layer; etching bit-linecontact openings in said first insulating layer to said first contactplugs; depositing a second polycide layer and a second cap layer andpatterning to form bit lines and forming insulating second sidewallspacers on said bit lines; etching capacitor node contact openings insaid first insulating layer to said first contact plugs; depositing asecond conducting layer composed of doped polysilicon; polishing backsaid second conducting layer to said second cap layer and patterningsaid second conducting layer to form second contact plugs for capacitornode contacts to said first contact plugs, said second contact plugsauto-self-aligned to said bit lines; depositing and planarizing a secondinsulating layer and etching openings for capacitor bottom electrodes tosaid second contact plugs; forming a third conducting layer in saidopenings for said capacitor bottom electrodes and forming aninterelectrode dielectric layer and a fourth conducting layer to formsaid capacitors and completing said array of high-density memory cells.15. The method of claim 14 , wherein said first polycide layer iscomposed of a doped polysilicon layer having a thickness of betweenabout 500 and 2000 Angstroms and an upper tungsten silicide layer havinga thickness of between about 500 and 1500 Angstroms.
 16. The method ofclaim 14 , wherein said first cap oxide layer is silicon oxide depositedby low-pressure chemical vapor deposition to a thickness of betweenabout 1000 and 2000 Angstroms.
 17. The method of claim 14 , wherein saidfirst sidewall spacers are silicon oxide and have a width of betweenabout 500 and 1000 Angstroms.
 18. The method of claim 14 , wherein saiddiffusion protection layer is silicon oxide deposited by chemical vapordeposition to a thickness of between about 100 and 500 Angstroms. 19.The method of claim 14 wherein said first conducting layer composed of apolysilicon layer is deposited by low-pressure chemical vapor depositionto a thickness sufficient to fill the recesses between said word lines,and is doped with an N type dopant to a concentration of between about1.0 E 20 and 1.0 E 22 atoms/cm³.
 20. The method of claim 14 , whereinsaid first insulating layer is silicon oxide deposited by low-pressurechemical vapor deposition and is polished to have a thickness of betweenabout 2000 and 4000 Angstroms over said FET gate electrodes.
 21. Themethod of claim 14 , wherein said second polycide layer is composed of adoped polysilicon layer having a thickness of between about 500 and 1000Angstroms and an upper tungsten silicide layer having a thickness ofbetween about 500 and 1500 Angstroms.
 22. The method of claim 14 ,wherein said second cap layer is silicon nitride deposited bylow-pressure chemical vapor deposition to a thickness of between about1000 and 2000 Angstroms.
 23. The method of claim 14 , wherein saidsecond sidewall spacers are formed by depositing a conformal layer ofsilicon oxynitride and anisotropically etching back to form said secondsidewall spacers having a width of between about 500 and 1500 Angstroms.24. The method of claim 14 , wherein said capacitor node contactopenings that are selectively etched in said first insulating layer tosaid first contact plugs are also selectively etched to said second caplayer and said second sidewall spacers to prevent electrical shorts tosaid bit lines.
 25. The method of claim 14 , wherein said secondconducting layer composed of a doped polysilicon layer is deposited bylow-pressure chemical vapor deposition to a thickness sufficient to fillthe recesses between said bit lines, and is doped with an N type dopantto a concentration of between about 1.0 E 22 and 1.0 E 22 atoms/cm³. 26.The method of claim 14 , wherein said second insulating layer is siliconoxide deposited by LPCVD and is planarized to have a thickness ofbetween about 2000 and 4000 Angstroms over said bit lines.
 27. An arrayof high-density memory cells having auto-self-aligned contacts for DRAMdevices on a semiconductor substrate comprising of: device areas formemory cells surrounded and electrically isolated by field oxide areason said substrate; a gate oxide on said device areas; a patterned firstpolycide layer with a first cap oxide layer for word lines extendingover said device areas for FET gate electrodes, and doped source/drainareas adjacent to said gate electrodes, and first sidewall spacers onsaid word lines; a patterned diffusion protection oxide with openingsfor contacts to said substrate; a patterned first conducting layer inrecesses between said word lines, providing first contact plugs that areauto-self-aligned to said gate electrodes; a planar first insulatinglayer with bit-line contact openings in said first insulating layer tosaid first contact plugs; a patterned second polycide layer with asilicon nitride second cap layer for bit lines and having insulatingsecond sidewall spacers on said bit lines; capacitor node contactopenings in said first insulating layer to said first contact plugs; apatterned second conducting layer in recesses between said bit lines,providing second contact plugs for capacitor node contacts that areauto-self-aligned to said bit lines; a planar second insulating layer onsaid bit lines with openings over and to said second contact plugs; athird conducting layer in said openings for capacitor bottom electrodes,an interelectrode dielectric layer and a fourth conducting layer on saidbottom electrode for capacitors.
 28. The DRAM structure of claim 27 ,wherein said first cap oxide is silicon oxide.
 29. The DRAM structure ofclaim 27 , wherein said diffusion protection layer is silicon oxide. 30.The DRAM structure of claim 27 , wherein said first and secondconducting layers are conductively doped polysilicon.
 31. The DRAMstructure of claim 27 , wherein said second cap layer and said secondsidewall spacers are silicon nitride.